This application is related to Japanese Patent Application No. 2000-208417 filed on Jul. 10, 2000, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process for producing a semiconductor device, and more particularly, it relates to a process for producing a semiconductor device in that a uniform polishing rate can be obtained irrespective to an element region width to enable planation of an element.
2. Description of Related Art
Along with progress of fine structures of elements, an element isolating region electrically isolating elements is also demanded to miniaturize. As a method for forming a minute element isolating region, a trench isolating method has been known, in which trenches are formed on a silicon substrate, and an dielectric film (such as an oxide film) is filled in the trenches.
Examples of a process for filling the trenches with the dielectric film include an LP-CVD process, an O3-TEOS CVD process and an HDP-CVD (high density plasma CVD) process.
FIG. 3 is a cross sectional view of a silicon substrate having an oxide film filled therein by the LP-CVD process or the O3-TEOS CVD process. In the figure, numeral 31 denotes a silicon substrate, 32 denotes an oxide film, and 33 denotes an SiN film. In these processes, the isolation dimension of the trenches is decreased along with the progress of fine structures of element of the semiconductor device, and thus the filling capability of the oxide film 35 is in short in the minute trenches, so as to cause a seam 34 (gap). Owing to the presence of the seam 34, dents are formed on the element isolating regions upon forming the semiconductor device, and a material of a gate electrode is accumulated in the dents to cause such a problem that a short circuit is formed among the gate electrodes.
In order to solve the problem, the HDP-CVD process has been widely employed. In the HDP-CVD process, an oxide film is formed, and simultaneously edges of the film thus formed are etched, so as to provide such characteristics that minute trenches can be filled.
FIG. 4 shows a cross sectional view of a silicon substrate after filling with an oxide film by the HDP-CVD process. In the figure, symbols W1, W2 and W3 denote widths of element regions, B1, B2 and B3 denote element forming regions, t denotes an accumulated thickness of an oxide film thus filled, numeral 41 denotes a silicon substrate, 42 denotes an oxide film, 43 denotes an SiN film, and 44 denotes an oxide film accumulated by the HDP-CVD process (hereinafter, referred to as an HDP-CVD oxide film). As shown in FIG. 4, the HDP-CVD oxide film 44 has an accumulation angle xcex8 on the element forming regions.
The element region widths W1 and W2 of the element forming regions B1 and B2 in FIG. 4 satisfy the equation:
W1 (W2) less than 2t/tan xcex8
and the element region width W3 of the element forming region B3 satisfies the equation:
W3 greater than 2t/tan xcex8
The dielectric film accumulated on the element forming regions will be described in detail below with reference to FIGS. 13 to 17.
In the following description, t denotes the accumulated thickness of the dielectric film, T denotes the depth of the trench, h denotes the accumulation height of the dielectric film on the element forming region, W denotes the element region width, and xcex8 denotes the accumulation angle of the dielectric film on the element forming region.
In the case of t less than T, a cross sectional view of an element forming region having an element region width W satisfying the equation:
Wxe2x89xa62t/tan xcex8
is shown in FIG. 13, and a cross sectional view of an element forming region having an element region width W satisfying the equation:
W greater than 2t/tan xcex8
is shown in FIG. 14.
As shown in FIG. 13, in the case of txe2x89xa7h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base W and a height h=(W tan xcex8)/2.
As shown in FIG. 14, in the case of t less than h, the dielectric film on the element forming region is in the form of a trapezoid having a lower base W, an upper base Wxe2x88x92(2t/tan xcex8) and a height t.
In the case of t greater than T, a cross sectional view of an element forming region having an element region width W satisfying the equation:
Wxe2x89xa62t/tan xcex8
is shown in FIG. 15, and a cross sectional view of an element forming region having an element region width W satisfying the equation:
W greater than 2t/tan xcex8
is shown in FIG. 16.
As shown in FIG. 15, in the case of Txe2x89xa7h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base Wxe2x88x922(txe2x88x92T)/tan xcex8 and a height ((W tan xcex8)/2)xe2x88x92(txe2x88x92T).
As shown in FIG. 16, in the case of T less than h, the dielectric film on the element forming region is in the form of a trapezoid having a lower base Wxe2x88x922(txe2x88x92T)/tan xcex8, an upper base Wxe2x88x922t/tan xcex8 and a height T.
A cross sectional view of an element forming region having an element region width W satisfying the equation:
W=2t/tan xcex8
is shown in FIG. 17. In the case of t=T=h, the dielectric film on the element forming region is in the form of an isosceles triangle having a base W and a height of t=T=h.
FIGS. 5(a) to 5(e) show a forming process of an oxide film by the HDP-CVD process.
An oxide film 52 and an SiN film 53 are formed on a silicon substrate 51. After coating a resist 54, on which element isolation regions are then opened by a know photolithography technique, the SiN film 53 and the oxide film 52 are removed by anisotropic dry etching, and trenches are formed on the silicon substrate 51 (FIG. 5(a)). After removing the resist 54 and subjecting the interior of the trenches to thermal oxidation, an HDP-CVD oxide film 55 is accumulated on the whole surface of the substrate (FIG. 5(b)) and is polished by the CMP (chemical mechanical polishing) process until the SiN film 53 is exposed to effect planation, whereby the element isolation regions are formed (FIG. 5(c)).
The planation by the CMP process is greatly affected by the element region width and the density of the element forming regions. Particularly, in the case shown in FIG. 5(d) where there are both the region 1, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film 55 satisfying the equation W greater than 2t/tan xcex8 are built up, and the region 2, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film 55 satisfying the equation Wxe2x89xa62t/tan xcex8 are built up, the polishing rate of the region 1 is smaller than that of the region 2. Therefore, the period of time required for removing by polishing the oxide film 55 in the region 1 is prolonged in comparison to the polishing period required by the region 2, and thus such a problem is developed that the oxide film in the region 2 is excessively polished when the oxide film in the region 1 is completely polished, so as to fail to obtain uniform heights after polishing (FIG. 5(e)).
In order to solve the problem, JP-A-11-214499 proposes the following process to avoid the non-uniformity in polishing process. Trenches are formed on a semiconductor substrate to form element forming regions and element isolating regions, and after accumulating an HDP-CVD oxide film, a mask pattern having openings on part of the element forming regions. The oxide film on the element forming regions is once removed according to the mask pattern, planation is then carried out.
FIGS. 6(a) to 6(e) show a forming process of element forming region according to JP-A-11-214499.
An oxide film 62 and an SiN film 63 are formed on a silicon substrate 61. After coating a resist 64 to form a first mask pattern, the SiN film 63 and the oxide film 62 are removed according to the first mask pattern by a known photolithography technique with anisotropic dry etching, and trenches are formed on the silicon substrate 61 (FIG. 6(a)). After removing the resist 64 and subjecting the interior of the trenches to thermal oxidation, an HDP-CVD oxide film 65 is accumulated on the whole surface of the substrate (FIG. 6(b)). A second mask pattern is formed to have openings on element forming regions that have a large element region width (FIG. 6(c)), and the HDP-CVD oxide film 65 is removed on the element forming regions according to the second mask pattern by dry etching (FIG. 6(d)). After removing the second mask pattern, the oxide film is polished by the CMP process until the SiN film 63 is exposed to effect planation of the wafer (FIG. 6(e)). The publication also discloses that the opening width of the second mask pattern is of a size of at least xc2xd of the minimum element region width. According to the process, while the planation degree of the wafer is improved, the filled oxide film is also thinned by erosion upon CMP process in the region where the stopper film on polishing (SiN film 63) occupies an area of more than a certain extent. Specifically, in the case where there are both the region 1, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film satisfying the equation W greater than 2t/tan xcex8 are built up, and the region 2, in which the element forming regions having the relationship between the element region width W and the accumulation thickness t of the oxide film satisfying the equation Wxe2x89xa62t/tan xcex8 are built up (FIG. 7(a)), removal of the oxide film according to the second mask pattern brings about the state shown in FIG. 7(b), and when the whole wafer is polished until the SiN film in the region 2 is exposed, the filled oxide film in the element isolating regions in the region 1 is also polished. As a result, a difference of the thickness of the filled oxide film is developed between the element isolating regions in the region 1 and the element isolating regions in the region 2 (FIG. 7(c)).
FIGS. 8 and 9 show a schematic cross sectional view of an element having a difference in thickness of a filled oxide film developed by polishing the whole wafer. The height from the surface of the silicone substrate to the surface of the filled oxide film (the surface of the element isolation region) in the region 1 is denoted by Ta, and the height from the surface of the silicone substrate to the surface of the element isolation region in the region 2 is denoted by Tb (Ta greater than Tb). The filled oxide film is further removed by the step of removing the nitride film and the oxide film that is carried out after polishing the whole wafer. The amount of removal of the filled oxide film at this time is denoted by Tc (FIG. 9).
In the case of Ta greater than Tc greater than Tb, the surface of the element isolation region is higher than the surface of the silicon substrate in the region 1 and is lower than the surface of the silicon substrate in the region 2. Thereafter, a gate oxide film and a gate electrode are formed (FIG. 10). FIG. 11 is a cross sectional view on line X-Xxe2x80x2 in FIG. 10 in the region 1. When the step between the surface of the element isolating region and the surface of the silicon substrate is large, a side wall 85 is formed with a material of the gate electrode on the side surface of the element isolating region to cause a problem of formation of a short circuit of electrodes between the elements A and B.
FIG. 12 is a cross sectional view on line Y-Yxe2x80x2 in FIG. 10 in the region 2. Because the surface of the element isolating region is lower than the surface of the silicon substrate, concentration of an electric field from the gate electrode 87 occurs at channel edges 86 to lower the threshold value at the channel edges, and thus such a problem arises that good transistor characteristics cannot be obtained.
In the case of Ta less than Tc and Tb less than Tc, all the surface of all the element isolating regions is lower than the surface of the silicon substrate. The similar problem as in the forgoing case is also developed in this case that concentration of an electric field occurs at the channel edges to fail to obtain good transistor characteristics. Furthermore, in the case of Ta greater than Tc and Tb greater than Tc, the over etching amount on processing the gate electrode is generally required to be the amount of Taxe2x88x92Tc. In this case, a sufficient selective ratio cannot be obtained when the thickness of the gate oxide film is decreased along with the progress of fine structures of elements, and therefore, the filled oxide film cannot be appropriately removed to make the electrode material remaining as a side wall, so as to bring about a problem of formation of a short circuit between the elements.
Accordingly, it is demanded that both Ta and Tb are slightly larger than Tc, and it is also demanded that the heights of the element isolating regions on silicon are uniform.
As described in the foregoing, there has been a problem in that when a difference is developed in the height of the filled oxide film, such problems occur that good transistor characteristics cannot be obtained, and the production process of the semiconductor device becomes complex. Under the circumstances, the inventors have found a process for producing a semiconductor device in that a uniform polishing rate can be obtained irrespective to an element region width to enable planation of an element, and thus the invention has been completed.
The present invention provides a process for producing a semiconductor device comprising plural element forming regions having different element region widths W and element isolating regions between said element forming regions,
said process comprising
a step of forming trenches on a semiconductor substrate having previously accumulated thereon a first dielectric film for forming said element isolating regions;
a step of accumulating a second dielectric film having a thickness t on said semiconductor substrate to fill in said trenches;
a step of removing part of said second dielectric film on said element forming regions that have an element regions width W satisfying the following equation:
Wxe2x89xa72t/tan xcex8
wherein xcex8 represents an accumulation angle of said second dielectric film on said element forming region; and
a step of polishing said second dielectric film by a CMP process.
The present invention provides a process for producing a semiconductor device comprising plural element forming regions having different element region widths W and element isolating regions between said element forming regions,
said process comprising
a step of forming a first dielectric film on a semiconductor substrate, and forming a first mask pattern on said element forming regions;
a step of removing said first dielectric film on said element isolating regions according to said first mask pattern, and forming trenches on said semiconductor substrate, by anisotropic etching;
a step of removing said first mask pattern, and accumulating a second dielectric film having a thickness t on said semiconductor substrate to fill in said trenches;
a step of forming a second mask pattern having openings on part of said second dielectric film on said element forming regions that have an element regions width W satisfying the following equation:
Wxe2x89xa72t/tan xcex8
wherein xcex8 represents an accumulation angle of said second dielectric film on said element forming region;
a step of removing said second dielectric film according to said second mask pattern by anisotropic etching; and
a step of removing said second mask pattern, and polishing said second dielectric film by a CMP process.